This invention relates to an ATM switching system and, more particularly, to an ATM switching system for converting a VPI/VCI included in the header of a cell to a cell address having a number of bits smaller than the number of bits of the VPI/VCI, and controlling the management of various data and the switching of cells based upon the cell address.
There is increasing demand not only for audio communication and data communication but also for multimedia communication in which moving pictures are transmitted as well as audio and data. B-ISDN (broadband-ISDN) switching technology, which is based upon an asynchronous transfer mode (ATM), is being put to practical use as a means for realizing broadband communication for multimedia communication.
In an ATM transmission system, all information is transferred at high speed upon being converted to fixed information referred to as cells or packetst More specifically, in an ATM transmission system, physical links are multiplexed on a physical line to thereby allocate the line to a plurality of calls. Moving-picture data or audio data from a terminal corresponding to each call are broken down into fixed-length information units (referred to as "cells or packets"), and the cells are transmitted over a line sequentially to realize multiplexing.
As shown in FIG. 23A, a cell is composed of a fixed-length block of 53 bytes of which five bytes constitute a header HD and 48 bytes an information field (payload) DT. In order that the destination will be understood even after data are broken down into blocks, the header HD includes a virtual channel identifier (VCI) for call identifying purposes. The header HD further includes a virtual path identifier (VPI) that identifies a path, a generic flow control (GFC) used in flow control between links, payload type (PT) and a head error control (HEC), which is a code for correcting errors in the header. A combination of VPI/VCI identifies a connection on which a cell is routed.
FIG. 24 is a diagram for describing an ATM switch, which has an ATM switch unit 1, a VCC (virtual channel converter) 2 and a call processor 3 for processing calls. The VCC 2 has VCC circuits 2.sub.1 .about.2.sub.3 corresponding to incoming lines #1.about.#3. Each VCC circuit adds a tag TAG (see FIG. 23B) onto a cell that has entered from the corresponding incoming line, replaces the VCI included in this cell with another VCI and then sends the cell to the ATM switch unit 1. When a call is originated, the call processor 3 performs call control, decides the VCI of the call, decides the tag for routing and writes the tag and the replacement VCI in a VCC table (not shown) of the VCC circuit in which the cell corresponding to the call enters. When call control is finished and the cell enters a prescribed incoming line via a higher ranking ATM switch, the VCC circuit connected to this incoming line reads control information (the tag TAG and VCI), which conforms to the VCI that has been added onto the input cell, from a routing table. The VCC circuit adds the tag TAG onto the cell, replaces the VCI of this tag with the VCI that has been read out and then sends the cell to the ATM switch unit 1. The latter switches the cell on the basis of the tag TAG so that the cell is sent to the prescribed outgoing line.
The ATM switch unit 1 includes tag information detection circuits I.sub.1 .about.I.sub.3, transmission information delay circuits D.sub.1 .about.D.sub.3, demultiplexers DM.sub.1 .about.DM.sub.3 and tag information decoding circuits DEC.sub.1 .about.DEC.sub.3, which construct a cell distribution unit CELD, buffer memories such as FIFO (first-in, first-out) memories FM.sub.11 .about.FM.sub.33, selectors SEL.sub.1 .about.SEL.sub.3, and arrival order management FIFOs AOM.sub.1 .about.AOM.sub.3. Each arrival order management FIFO (AOM.sub.1 .about.AOM.sub.3) is connected to the output terminals of the information decoding circuits DEC.sub.1 .about.DEC.sub.3 and stores the order in which cells arrive at the corresponding three buffer memories FM.sub.11 .about.FM.sub.13, FM.sub.21 .about.FM.sub.23, FM.sub.31 .about.FM.sub.33. These FIFOs control the corresponding selectors SEL.sub.1 .about.SEL.sub.3 so that cells are read out of the three buffer memories in the order of cell arrival and sent to outgoing lines #1.about.#3.
A cell which enters the ATM switch unit 1 has the structure shown in FIG. 23B. The detection circuits I.sub.i (i=1.about.3) extract the tag information contained in the input signal and send the information to the decoder circuits DECI (i=1.about.3). If the entering tag information TAG indicates the output terminal #j (j=1.about.3), the decoder circuit DEC.sub.i operates the demultiplexer DM.sub.i by a changeover signal S.sub.i to send the transmission information to the FIFO memory FM.sub.ji. For example, if the tag TAG contained in the cell which has entered from the input terminal #1 indicates output terminal #2, the decoder circuit DEC.sub.1 operates the demultiplexer DM.sub.1 so that the information from the input terminal #1 enters FIFO FM.sub.21.
The arrival order management FIFOs (AOM.sub.i .about.AOM.sub.3) are each connected to the output terminals of the tag information decoding circuits DEC.sub.1 .about.DEC.sub.3 and store the order in which cells arrive at the corresponding three buffer memories FM.sub.11 .about.FM.sub.33, FM.sub.21 .about.FM.sub.23, FM.sub.31 .about.FM.sub.33. For example, if cells arrive in the order of buffer memories FM.sub.11 .fwdarw.FM.sub.12 .fwdarw.FM.sub.13 .fwdarw.FM.sub.12 .fwdarw. . . . , buffer memory identification codes are stored in the arrival order management FIFOs (AOM.sub.i .about.AOM.sub.3) in the order of cell arrival, i.e., in the manner 1.fwdarw.2.fwdarw.3.fwdarw.2.fwdarw. . . . . Thereafter, the arrival order management FIFOs (AOM.sub.i .about.AOM.sub.3) control the corresponding selectors SEL.sub.1 .about.SEL.sub.3 so that cells are read out of the three buffer memories FM.sub.11 .about.FM.sub.33, FM.sub.21 .about.FM.sub.23, FM.sub.31 .about.FM.sub.33 in the order of cell arrival and sent to the outgoing lines #1.about.#3.
A buffer function is thus obtained by providing each buffer memory FM.sub.ij with a capacity equivalent to a plurality of cells. This makes it possible to deal satisfactorily with a case in which there is a temporary increase in transmission data. Further, since cells are read out of the buffer memories FM.sub.i1 .about.FM.sub.i3 (FM.sub.11 .about.FM.sub.33, FM.sub.21 .about.FM.sub.23, FM.sub.31 .about.FM.sub.33) in the order of cell arrival, equal numbers of cells reside in the buffer memories FM.sub.i1 .about.FM.sub.i3. This makes it possible to eliminate situations in which cells are discarded owing to overflow of the buffer memories.
Though not illustrated, a number of subscriber interface units or line interface units connected to transmission lines and a line concentrator for concentrating cells, which are output by the subscriber interface units or line interface units, and entering the cells into the VCC lines 2.sub.1 .about.2.sub.3, are provided at the input stage to the VCC circuits 2.sub.1 .about.2.sub.3. Further, The outgoing lines #1.about.#3 of the ATM switch 1 are provided with a line deconcentrator for deconcentrating cells, which have entered from the ATM switch unit 1, on a per-subscriber interface basis or per line interface basis, and entering the cells into the interface units.
The ATM switch, which is a system which performs switching in units of the VPI/VCI contained in the cell headers, carries out UPC (Usage Parameter Control), billing control and other processing based upon the VPI/VCI value. In accordance with recommendations, the VPI/VCI is represented by a total of 28 bits (the VPI is 12 bits and the VCI is 16 bits). However, depending upon the ATM switching system, it is often unnecessary to manage a large volume of connections of VPI+VCI=28 bits simultaneously. In the prior art, however, various processing and switching operations are executed based upon a VPI/VCI of 28 bits even in such case. As a result, various tables and processing circuits are unnecessarily large, thereby raising the cost of the ATM switching system.
In order to make it possible to continue service even in the event of a failure, it has been contemplated to provide redundancy for the subscriber interfaces or line interfaces in an ATM switching system (the following discussion will deal with subscriber interfaces). In such case the line concentrator is required to concentrate only cells output by the active subscriber interfaces and enter these cells into the ATM switch unit. More specifically, it is required that the line concentrator concentrate cells upon deleting cells output by the standby subscriber interfaces. On the other hand, when the deconcentrator deconcentrates cells, which are output by the ATM switch unit, on a per-active subscriber interface basis and sends the cells to the subscriber interface, the deconcentrator must send the cells to the standby subscriber interfaces as well. The problem which arises in the prior art is that control for concentrating cells and for deconcentrating cells cannot be performed in simple fashion in a case where such active and standby subscriber interfaces exist.
Further, in various ATM products, the foremost of which is the ATM switch, the cell concentrator and deconcentrator are important functional elements that decide performance. Consequently, there is demand for a line concentrator and deconcentrator capable of implementing the line concentration and deconcentration required in an ATM switching system.